In FIG. 1 we show a schematic view of a Field Effect Transistor (FET) of the Lightly Doped Drain (LDD) type. Polysilicon gate 2 lies on P-type silicon substrate 1 with gate insulation layer 3 between them. The gate is used to control current flow between the two N-type regions 4 one of which serves as a source while the other serves as a drain. To improve performance of the device, region 4 does not interface directly with P material 1 under the gate. Instead 4 connects to region 5 which is both thinner and more lightly doped than region 4.
To make this structure, region 5 is formed first by ion implantation, using gate 2 as a mask. Then, dielectric spacers 6 are formed on the vertical sidewalls of 2 and region 4 is formed using a second ion implantation, with the spacers now serving as the mask.
It is also necessary to electrically isolate the device from other electrical components on the same P substrate. This is often done by means of shallow trench isolation (STI). Trench 7 having gently sloping walls (at a typical angle of about 80 degrees from the vertical) is formed using standard etching techniques and then back filled with a dielectric material (usually silicon oxide).
To make electrical contact to the source, gate, and drain regions, the Self Aligned Silicide (SALICIDE) process is used. A layer of metal such as titanium is deposited over all surfaces and then given a brief, but intense, heat treatment or Rapid Thermal Anneal (RTA) which is sufficient to cause the titanium to react with all silicon surfaces with which it is in contact, thereby getting converted to titanium silicide. The titanium does not react with any of the non-silicon surfaces that it contacts such as the spacers and the shallow isolation trench. Thus, following the RTA, a selective etch may be used to remove all unreacted titanium while leaving behind the titanium silicide. The latter is a good electrical conductor so the net result is separate contacts to the source and drain, separated from the gate contact by the spacers. Similarly, no titanium silicide will form on the top surface of the isolation trench 7 so it continues to function in this capacity.
As part of subsequent processing, it is often necessary to lay down a thin (about 350 Angstrom) oxide layer on the structure of FIG. 1 followed by a removal etch. For example, I/O circuitry present elsewhere on the surface (not shown) need to be protected by a layer of oxide prior to titanium deposition in order to improve ESD performance. This resist protection oxide (RPO) is formed by protecting the appropriate area with photoresist and then etching unprotected areas in the usual way. This results in the removal of about 350-400 Angstroms of any unprotected oxide, including the surface of the oxide that was used to fill trench 7. Also, it is often necessary to remove native oxide (or even all remaining oxide) prior to the formation of silicide surfaces. A `pre-Ti sputter` etch (usually HF solution) is normally performed. This results in the removal of 50-100 Angstroms of the oxide that was used to fill trench 7.
The appearance of the structure of FIG. 1 after RPO etch and `pre-Ti sputter` etch is shown in FIG. 2. As shown, the top surface of the trench filler oxide material has now dropped below the top surface of layer 4 that is adjacent to it. The step in the surface that is formed as a result of this has an exposed vertical edge that is pointed to by arrow 22. Bearing in mind that, during the SALICIDE step that follows, titanium silicide will form on the newly exposed vertical edge 22, it is apparent that only a very thin layer of N-type silicon in region 4 remains between titanium silicide that forms on 22 and P-type silicon region 1. Thus the possibility that source/drain region 4 may short to the main substrate is increased substantially.
Another possible source of shorting via a titanium silicide bridge is also present. In this case, the short is between the source and the gate or between the drain and the gate. It will occur if a small amount of titanium silicide is formed on either of the spacers as a result of some diffusion of silicon to the surface of the spacer during the RTA. The present invention seeks to provide a process and structure that eliminates both type of short.
Prior art that we have come across and that may have some bearing on the present invention includes Yamauchi (U.S. Pat. No. 5,424,232 June 1995) who describes a non-volatile memory based on a floating gate. Part of the structure that is shown by Yamauchi includes silicon nitride spacers on the vertical sides of the floating gate, said spacers extending upwards to some point that is higher than the gate.
Douglas (U.S. Pat. No. 4,916,511 April 1990) teaches a method for etching a deep trench in silicon for use in a capacitor structure having positively sloped, but steep, sidewalls and a flat bottom.
Tamaki et al. (U.S. Pat. No. 4,635,090 January 1987) show how to make a trench having walls that are vertical for their lower half and positively sloping for the upper half.